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White Electronic Designs
WF128K32-XXX5
128KX32 5V FLASH MODULE, SMD 5962-94716
FEATURES
Access Times of 50**, 60, 70, 90, 120, 150ns Packaging: * * 66 pin, PGA Type, 1.075 inch square, Hermetic Ceramic HIP (Package 400) 68 lead, Hermetic CQFP (G2U), 22.4mm (0.880 inch) square, 3.56mm (0.140 inch) high (Package 510) 68 lead, Hermetic CQFP (G2L), 22.4mm (0.880 inch) square, 4.06mm (0.160 inch) high (Package 528) 8 equal size sectors of 16KBytes each Any combination of sectors can be concurrently erased. Also supports full chip erase Commercial, Industrial and Military Temperature Ranges 5 Volt Programming. 5V 10% Supply Low Power CMOS, 1mA Standby Typical Embedded Erase and Program Algorithms TTL Compatible Inputs and CMOS Outputs Built-in Decoupling Caps and Multiple Ground Pins for Low Noise Operation Page Program Operation and Internal Program Control Time Weight WF128K32-XG2LX5 - 8 grams typical WF128K32-XG2UX5 - 8 grams typical WF128K32-XH1X5 - 13 grams typical
Note: For programming information refer to Flash Programming 1M5 Application Note. * This product is subject to change without notice. * * The access time of 50ns is available in Industrial and Commercial temperature ranges only.
*
Sector Architecture * *
100,000 Erase/Program Cycles Typical, 0C to +70C Organized as 128Kx32
FIGURE 1 - PIN CONFIGURATION FOR WF128K32N-XH1X5 Top View
I/O8 I/O9 I/O10 A14 A16 A11 A0 NC I/O0 I/O1 I/O2 WE2# CS2# GND I/O11 A10 A9 A15 VCC CS1# NC I/O3 I/O15 I/O14 I/O13 I/O12 OE# NC WE1# I/O7 I/O6 I/O5 I/O4 I/O24 I/O25 I/O26 A7 A12 NC A13 A8 I/O16 I/O17 I/O18 VCC CS4# WE4# I/O27 A4 A5 A6 WE3# CS3# GND I/O19 I/O31 I/O30 I/O29 I/O28 A1 A2 A3 I/O23 I/O22 I/O21
8 8 8 8 OE# A0-16
Pin Description
I/O0-31 A0-16 WE1-4# CS1-4# OE# VCC GND NC Data Inputs/Outputs Address Inputs Write Enables Chip Selects Output Enable Power Supply Ground Not Connected
Block Diagram
WE1# CS1# WE2# CS2# WE3# CS3# WE4# CS4#
128K x 8
128K x 8
128K x 8
128K x 8
I/O20
I/O0-7 I/O8-15 I/O16-23 I/O24-31
March 2006 Rev. 8
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White Electronic Designs
WF128K32-XXX5
FIGURE 3 - PIN CONFIGURATION FOR WF128K32-XG2UX5 AND WF128K32-XG2LX5
TOP VIEW
NC A0 A1 A2 A3 A4 A5 CS3# GND CS4# WE1# A6 A7 A8 A9 A10 VCC
PIN DESCRIPTION
I/O0-31 A0-16 WE1-4# CS1-4# OE# VCC GND NC Data Inputs/Outputs Address Inputs Write Enables Chip Selects Output Enable Power Supply Ground Not Connected
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 GND I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 VCC A11 A12 A13 A14 A15 A16 CS1# OE# CS2# NC WE4# WE3# WE2# NC NC NC I/O16 I/O17 I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 GND I/O24 I/O25 I/O26 I/O27 I/O28 I/O29 I/O30 I/O31
BLOCK DIAGRAM
WE1# CS1# WE2# CS2# WE3# CS3# WE4# CS4#
OE# A0-16
128K x 8
128K x 8
128K x 8
128K x 8
8
8
8
8
I/O0-7
I/O8-15
I/O16-23
I/O24-31
March 2006 Rev. 8
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ABSOLUTE MAXIMUM RATINGS (1)
Parameter Operating Temperature Supply Voltage Range (VCC) Signal voltage range (any pin except A9) (2) Storage Temperature Range Lead Temperature (soldering, 10 seconds) Data Retention Mil Temp Endurance (write/erase cycles) Mil Temp
A9 Voltage for sector protect (VID) (3)
WF128K32-XXX5
RECOMMENDED OPERATING CONDITIONS
Unit C V V C C Parameter Supply Voltage Input High Voltage Input Low Voltage Operating Temp. (Mil.) A9 Voltage for Sector Protect Symbol VCC VIH VIL TA VID Min 4.5 2.0 -0.5 -55 11.5 Max 5.5 VCC + 0.3 +0.8 +125 12.5 Unit V V V C V
-55 to +125 -2.0 to +7.0 -2.0 to +7.0 -65 to +150 +300 10 years 10,000 cycles min.
-2.0 to +14.0
V
NOTES: 1. Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 2. Minimum DC voltage on input or I/O pins is -0.5V. During voltage transitions, inputs may overshoot VSS to -2.0 V for periods of up to 20ns. Maximum DC voltage on output and I/O pins is Vcc + 0.5V. During voltage transitions, outputs may overshoot to VCC + 2.0 V for periods of up to 20ns. 3. Minimum DC input voltage on A9 pin is -0.5V. During voltage transitions, A9 may overshoot Vss to -2V for periods of up to 20ns. Maximum DC input voltage on A9 is +13.5V which may overshoot to 14.0 V for periods up to 20ns.
CAPACITANCE
Ta = +25C Parameter OE# capacitance WE1-4# capacitance HIP (PGA) H1 CQFP G2U/G2L CS1-4# capacitance Data# I/O capacitance Address input capacitance Symbol Conditions COE VIN = 0V, f = 1.0 MHz CWE VIN = 0V, f = 1.0 MHz Max Unit 50 pF pF 20 15 VIN = 0V, f = 1.0 MHz 20 pF VI/O = 0V, f = 1.0 MHz 20 pF VIN = 0V, f = 1.0 MHz 50 pF
CCS CI/O CAD
This parameter is guaranteed by design but not tested.
DC CHARACTERISTICS - CMOS COMPATIBLE
VCC = 5.0V, VSS = 0V, -55C TA +125C Parameter Input Leakage Current Output Leakage Current VCC Active Current for Read (1) VCC Active Current for Program or Erase (2) VCC Standby Current VCC Static Current Output Low Voltage Output High Voltage Output High Voltage Low VCC Lock Out Voltage Symbol ILI ILOx32 ICC1 ICC2 ICC3 ICC4 VOL VOH1 VOH2 VLKO Conditions VCC = 5.5, VIN = GND to VCC VCC = 5.5, VIN = GND to VCC CS# = VIL, OE# = VIH CS# = VIL, OE# = VIH VCC = 5.5, CS# = VIH, f = 5MHz VCC = 5.5, CS# = VIH IOL = 8.0 mA, VCC = 4.5 IOH = -2.5 mA, VCC = 4.5 IOH = -100 A, VCC = 4.5 Min Max 10 10 140 200 6.5 0.6 0.45 0.85 x VCC VCC -0.4 3.2 Unit A A mA mA mA mA V V V V
NOTES: 1. The ICC current listed includes both the DC operating current and the frequency dependent component (at 5 MHz). The frequency component typically is less than 2 mA/MHz, with OE# at VIH. 2. ICC active while Embedded Algorithm (program or erase) is in progress. 3. DC test conditions: VIL = 0.3V, VIH = VCC - 0.3V
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VCC = 5.0V, VSS = 0V, -55C TA +125C Parameter Write Cycle Time WE# Setup Time CS# Pulse Width Address Setup Time Data Setup Time Data Hold Time Address Hold Time WE# Hold from WE# High CS# Pulse Width High Duration of Programming Operation Duration of Erase Operation Read Recovery before Write Chip Programming Time Symbol Min tAVAV tWLEL tELEH tAVEL tDVEH tEHDX tELAX tEHWH tEHEL tWHWH1 tWHWH2 tGHEL tWC tWS tCP tAS tDS tDH tAH tWH tCPH 50 0 25 0 25 0 40 0 20 14 2.2 0 12.5 60 -50 Max Min 60 0 30 0 30 0 45 0 20 14 2.2 0 12.5 60 -60 Max Min 70 0 35 0 30 0 45 0 20 14 2.2 0 12.5 60 -70 Max Min 90 0 45 0 45 0 45 0 20 14 2.2 0 60 -90
WF128K32-XXX5
AC CHARACTERISTICS - WRITE/ERASE/PROGRAM OPERATIONS, CS# CONTROLLED
-120 Min Max 120 0 50 0 50 0 50 0 20 14 2.2 0 12.5 12.5 60 -150 Min Max 150 0 50 0 50 0 50 0 20 14 2.2 0 12.5 60 Unit ns ns ns ns ns ns ns ns ns s sec ns sec
Max
FIGURE 4 - AC TEST CIRCUIT AC Test Conditions
Parameter Input Pulse Levels Input Rise and Fall Input and Output Reference Level Output Timing Reference Level Typ VIL = 0, VIH = 3.0 5 1.5 1.5 Unit V ns V V
Notes: VZ is programmable from -2V to +7V. IOL & IOH programmable from 0 to 16mA. Tester Impedance Z0 = 75 . VZ is typically the midpoint of VOH and VOL. IOL & IOH are adjusted to simulate a typical resistive load circuit. ATE tester includes jig capacitance.
March 2006 Rev. 8
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VCC = 5.0V, VSS = 0V, -55C TA +125C Parameter Write Cycle Time Chip Select Setup Time Write Enable Pulse Width Address Setup Time Data Setup Time Data Hold Time Address Hold Time Chip Select Hold Time Write Enable Pulse Width High Duration of Byte Programming Operation (min) Sector Erase Time Read Recovery Time Before Write VCC Setup Time Chip Programming Time Output Enable Setup Time Output Enable Hold Time (1)
1. For Toggle and Data Polling.
WF128K32-XXX5
AC CHARACTERISTICS - WRITE/ERASE/PROGRAM OPERATIONS, WE# CONTROLLED
Symbol Min tAVAV tELWL tWLWH tAVWL tDVWH tWHDX tWLAX tWHEH tWC tCS tWP tAS tDS tDH tAH tCH 50 0 25 0 25 0 40 0 20 14 2.2 0 tVCS 50 12.5 tOES tOEH 0 10 0 10 60 -50 Max Min 60 0 30 0 30 0 45 0 20 14 2.2 0 50 12.5 0 10 60 -60 Max Min 70 0 35 0 30 0 45 0 20 14 2.2 0 50 12.5 0 10 60 -70 Max Min 90 0 45 0 45 0 45 0 20 14 2.2 0 50 12.5 0 10 60 -90 Max -120 Min Max 120 0 50 0 50 0 50 0 20 14 2.2 0 50 12.5 0 10 60 -150 Min Max 150 0 50 0 50 0 50 0 20 14 2.2 0 50 12.5 60 Unit ns ns ns ns ns ns ns ns ns s sec ns s sec ns ns
tWHWL tWPH tWHWH1 tWHWH2 tGHWL
AC CHARACTERISTICS - READ ONLY OPERATIONS
VCC = 5.0V, VSS = 0V, -55C TA +125C Parameter Read Cycle Time Address Access Time Chip Select Access Time OE# to Output Valid Chip Select to Output High Z (1) OE# High to Output High Z (1) Output Hold from Address, CS# or OE# Change, whichever is first
1. Guaranteed by design, not tested.
Symbol Min tAVAV tAVQV tELQV tGLQV tEHQZ tGHQZ tAXQX tRC tACC tCE tOE tDF tDF tOH 0 50
-50 Max Min 60 50 50 25 20 20 0
-60 Max Min 70 60 60 30 20 20 0
-70 Max Min 90 70 70 35 20 20 0
-90 Max
-120 Min Max 120
-150 Min Max 150
Unit ns
90 90 40 25 25 0
120 120 50 30 30 0
150 150 55 35 35
ns ns ns ns ns ns
March 2006 Rev. 8
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WF128K32-XXX5
FIGURE 5 - AC WAVEFORMS FOR READ OPERATIONS
tRC Addresses DX tACC CS1#/CS2# tDF OE# tOE Addresses Stable
WE#
tCE
tOH High Z
Outputs
DX
High Z
Output Valid
March 2006 Rev. 8
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WF128K32-XXX5
FIGURE 6 - WRITE/ERASE/PROGRAM OPERATION, WE# CONTROLLED
Data# Polling Addresses 5555H tWC CS# tGHWL OE# tWP WE# tCS tWPH tDH Data tDS tOH AOH PD D7# DOUT tOE tDF tWHWH1 tAS PA tAH PA tRC
5.0 V tCE
NOTES: 1. PA is the address of the memory location to be programmed. 2. PD is the data to be programmed at byte address. 3. D7# is the output of the complement of the data written to the device (for each chip). 4. DOUT is the output of the data written to the device. 5. Figure indicates last two bus cycles of four bus cycle sequence.
March 2006 Rev. 8
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WF128K32-XXX5
FIGURE 7 - AC WAVEFORMS CHIP/SECTOR ERASE OPERATIONS
tAH Addresses 5555H tAS CS# tGHWL OE# tWP WE# tWPH tCS tDH 2AAAH 5555H 5555H 2AAAH SA
Data tDS
AAH
55H
80H
AAH
55H
10H/30H
VCC
tVDS
Notes: 1. SA is the sector address for Sector Erase.
March 2006 Rev. 8
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WF128K32-XXX5
FIGURE 8 - AC WAVEFORMS FOR DATA# POLLING DURING EMBEDDED ALGORITHM OPERATIONS
CS#
tCH tDF tOE
OE# tOEH WE#
tCE
tOH High Z
D7 Data D0-D6 tWHWH 1 or 2
D7#
D7 = Valid Data
D0-D6 = Invalid tOE
D0-D7 Valid Data
March 2006 Rev. 8
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WF128K32-XXX5
FIGURE 9 - WRITE/ERASE/PROGRAM OPERATION, CS# CONTROLLED
Data# Polling Addresses 5555H tWC WE# tGHEL OE# tCP CS# tWS tWHWH1 tAS PA tAH PA
tCPH tDH
Data tDS
AOH
PD
D7#
DOUT
5.0 V
NOTES: 1. PA represents the address of the memory location to be programmed. 2. PD represents the data to be programmed at byte address. 3. D7# is the output of the complement of the data written to the device (for each chip). 4. DOUT is the output of the data written to the device. 5. Figure indicates the last two bus cycles of a four bus cycle sequence.
March 2006 Rev. 8
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WF128K32-XXX5
PACKAGE 400: 66 PIN, PGA TYPE, CERAMIC HEX-IN-LINE PACKAGE, HIP (H1)
4.60 (0.181)
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
March 2006 Rev. 8
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WF128K32-XXX5
PACKAGE 510: 68 LEAD, CERAMIC QUAD FLAT PACK, CQFP (G2U)
o
o
The White 68 lead G2U CQFP fills the same fit and function as the JEDEC 68 lead CQFJ or 68 PLCC. But the G2U has the TCE and lead inspection advantage of the CQFP form.
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
March 2006 Rev. 8
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WF128K32-XXX5
PACKAGE 528 : 68 LEAD, CERAMIC QUAD FLAT PACK, CQFP (G2L)
25.15 (0.990) 0.25 (0.010) MAX 22.36 (0.880) 0.25 (0.010) MAX
5.10 (0.200) MAX 0.25 (0.010) 0.10 (0.002)
0.23 (0.009) REF
24.0 (0.946) 0.25 (0.010) 2O / 9O
R 0.127 (0.005)
1.37 (0.054) MIN
0.004
0.89 (0.035) 1.14 (0.045)
1.27 (0.050) TYP 0.38 (0.015) 0.05 (0.002) 20.31 (0.800) REF
0.940" TYP
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
March 2006 Rev. 8
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ORDERING INFORMATION
WF128K32-XXX5
W F 128K32 X - XXX X X 5 X
LEAD FINISH: Blank = Gold plated leads A = Solder dip leads VPP PROGRAMMING VOLTAGE 5 = 5V DEVICE GRADE: Q = MIL - STD 833 Compliant M = Military Screened -55C to +125C I = Industrial -40C to +85C C = Commercial 0C to + 70C PACKAGE TYPE: H1 = 1.075" sq. Ceramic Hex In-line Package, HIP (Package 400) G2U = 22.4mm Ceramic Quad Flat Pack, Low Profile CQFP (Package 510) G2L = 22.4mm Ceramic Quad Flat Pack, Low Profile CQFP (Package 528)
ACCESS TIME (ns) IMPROVEMENT MARK N = No Connect at pin 8, 21, 28 and 39 in HIP for Upgrade ORGANIZATION, 128K x 32 User configurable as 256K x 16 or 512K x 8 Flash WHITE ELECTRONIC DESIGNS CORP.
March 2006 Rev. 8
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DEVICE TYPE
128K x 32 Flash 128K x 32 Flash 128K x 32 Flash 128K x 32 Flash 128K x 32 Flash
WF128K32-XXX5
SPEED
150ns 120ns 90ns 70ns 60ns
PACKAGE
66 pin HIP (H1) 66 pin HIP (H1) 66 pin HIP (H1) 66 pin HIP (H1) 66 pin HIP (H1)
SMD NO.
5962-94716 01H8X 5962-94716 02H8X 5962-94716 03H8X 5962-94716 04H8X 5962-94716 05H8X
128K x 32 Flash 128K x 32 Flash 128K x 32 Flash 128K x 32 Flash 128K x 32 Flash
150ns 120ns 90ns 70ns 60ns
68 lead CQFP (G2U) 68 lead CQFP (G2U) 68 lead CQFP (G2U) 68 lead CQFP (G2U) 68 lead CQFP (G2U)
5962-94716 01HNX 5962-94716 02HNX 5962-94716 03HNX 5962-94716 04HNX 5962-94716 05HNX
128K x 32 Flash 128K x 32 Flash 128K x 32 Flash 128K x 32 Flash 128K x 32 Flash
150ns 120ns 90ns 70ns 60ns
68 lead CQFP (G2L) 68 lead CQFP (G2L) 68 lead CQFP (G2L) 68 lead CQFP (G2L) 68 lead CQFP (G2L)
5962-94716 01HAX 5962-94716 02HAX 5962-94716 03HAX 5962-94716 04HAX 5962-94716 05HAX
Note 1: Package Not Recommended For New Design
March 2006 Rev. 8
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